1. Field of the Invention
This invention is generally directed to the field of semiconductor processing, and, more particularly, to a method of monitoring anneal processes performed on implant regions, and a system for performing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
During the course of manufacturing integrated circuit devices, a variety of doped regions may be formed in a semiconducting substrate. Typically, these doped regions are formed by performing an ion implant process wherein a dopant material, e.g., arsenic, phosphorous, boron, boron difluoride, etc., is implanted into localized areas of the substrate. For example, for CMOS technology, various doped regions, sometimes referred to as wells, are formed in the substrate. The wells may be formed using either N-type or P-type dopant atoms. After the wells are formed, semiconductor devices, e.g., transistors, may be formed in the region defined by the well. Of course, other types of doped regions may also be formed in modem semiconductor manufacturing operations.
As modem device dimensions continue to shrink, the implant profiles of the various doped regions become very important. That is, as device dimensions shrink, parameters of the doped region, such as depth, width, dopant concentration profile, etc., become more important. Small variations in one or more of these parameters may adversely affect device performance. For example, if well implants in a given device are formed too shallow or not formed deep enough, the devices formed in the wells may exhibit excessive leakage currents.
After implant regions are formed in a substrate, one or more anneal processes are performed to activate the implanted dopant atoms and to repair the damage to the lattice structure due to the ion implantation process. The temperature and duration of the anneal process may vary depending on the application. Moreover, the anneal process may be performed in either a furnace or a rapid thermal anneal (RTA) chamber. For example, where an RTA chamber is employed, the anneal process may be performed at a temperature ranging from approximately 1000-1200° C. for a duration anywhere from 10 seconds to 2 minutes.
During this anneal process, the implanted dopant atoms tend to migrate within the substrate in an approximately isotropic fashion.
The effectiveness of such anneal processing is normally monitored in an effort to insure that the implant regions are correctly formed such that they may function as intended. For example, for CMOS technology, various doped regions, sometimes referred to as wells, arc formed in the substrate. The wells may be formed using either N-type or P-type dopant atoms. After the wells are formed, semiconductor devices, e.g., transistors, may be formed in the region defined by the well. Of course, other types of doped regions may also be formed in modem semiconductor manufacturing operations.
As modern device dimensions continue to shrink, the implant profiles of the various doped regions become very important. That is, as device dimensions shrink, parameters of the doped region, such as depth, width, dopant concentration profile, etc., become more important. Small variations in one or more of these parameters may adversely affect device performance. For example, if well implants in a given device are formed too shallow or not formed deep enough, the devices formed in the wells may exhibit excessive leakage currents.
After implant regions are formed in a substrate, one or more anneal processes are performed to activate the implanted dopant atoms and to repair the damage to the lattice structure due to the ion implantation process. The temperature and duration of the anneal process may vary depending on the application. Moreover, the anneal process may be performed in either a furnace or a rapid thermal anneal (RTA) chamber. For example, where an RTA chamber is employed, the anneal process may be performed at a temperature ranging from approximately 1000-1200° C. for a duration of approximately 5-10 seconds. During this anneal process, the implanted dopant atoms tend to migrate within the substrate in an approximately isotropic fashion.
The effectiveness of such anneal processing is normally monitored in an effort to insure that the implant regions are correctly formed such that they may function as intended. To that end, one or more electrical tests may be performed to monitor the efficiency of the anneal process. In one example, one or more sheet resistance tests may be performed on one or more implant regions after the anneal process is performed, and from those results, the effectiveness of the anneal process is inferred. That is, for example, if, after the anneal process is performed, the implant region exhibits a sheet resistance value within certain limits, then the anneal process is deemed to be successful. Other electrical tests may be performed on the implant regions after the anneal process is performed to determine the effectiveness of the anneal process, e.g., capacitance-voltage measurement to determine the dopant profile. Parameters such as the depth of the implant regions may also be determined by employing various physical measurement techniques, e.g., so-called angle lap and stain techniques, groove and stain techniques, etc. In some cases, the implant regions may be cross-sectioned and inspected with the aid of microscopes. Moreover, in some cases, test wafers are manufactured for the purpose of performing such tests.
While the aforementioned techniques may be useful, they do have some drawbacks. For example, such testing can be very time-consuming, and the results of such testing may not be available as quickly as would otherwise be desired. Moreover, in some cases, the resulting profile of the implant region is assumed based upon the measurement results, e.g., resistance. That is, the testing methodology does not, in some cases, provide for direct measurement of the profile of the implant region; rather, such profile is inferred based upon the results of the test data.
The present invention is directed to various methods that may solve, or reduce, at least some of the problems described above.